1. Technical Field
The present invention relates to a method of manufacturing a semiconductor device.
2. Related Art
With further advancement in integration level and higher operation speed of devices, a demand has arisen in the lithographic process, in particular in a step of forming the gate pattern, with respect to formation of fine gate patterns far shorter than the wavelength of exposure light. It is very difficult to form fine patterns equal to or smaller than half of the wavelength of exposure light, so that various resolution enhancement techniques are under discussion.
Patent Document 1 (Japanese Laid-Open Patent Publication No. 2005-201967) describes a technique using the Levenson-type phase shift mask (PSM). The Levenson-type PSM is particularly excellent in effects of improving optical contrast and resolution performance, and is supposed to be an expectant technique of forming fine patterns equal to or smaller than half of the wavelength of exposure light. Phase shifters so as to change phase of transmitted light (through the phase shifters) by π are disposed on the Levenson-type PSM. The light intensity becomes zero at the bounadry between phase-shifter area and non-shifter area by complete canceling of positive-negative (0-π) photo-electric fields based on optical interference.
Patent Document 1 describes a configuration having gate electrodes of transistors agreed with respect to the longitudinal direction thereof. The document also describes procedures by which the gate electrode pattern is formed so as to extend to the end of the block in the longitudinal direction, and an unnecessary portion of the extended pattern is then removed. The procedures can realize a 0-π alternative arrangement of the shifters of the Levenson-type PSM, and can thereby suppress influences of setback of the line end and corner rounding of the gate patterns.
The Levenson-type PSM is, however, based on an image-forming method making an intentional use of interference of light wave using a small σillumination, so that influences of proximity effects (dense-scarce dependence of dimension, constriction, corner rounding, etc.) ascribable to interference of light become large by principle. A distinct dimensional variation occurs particularly in the gates adjacent to contact pads and so forth. There has conventionally been a well-known technique, OPC (optical proximity correction), modifying a mask pattern in order to obtain the designed pattern shape on a wafer, by taking the proximity effect into consideration. Increased complexity in the circuit pattern has, however, raised a problem of complicating the OPC, and of consequently increasing the operation load. Complicated circuit pattern has degraded the accuracy of correction, and resulting in the electrical characteristics of fabricated devices.
Patent Document 2 (Japanese Laid-Open Patent Publication No. 2005-86119) describes a method of forming a fine pattern, aimed at fabricating a photomask having a transmission portion and intercepting portion for light exposure onto a photo resist film, the method including a step of extracting regions where line portions and contact portions of a pattern of a photomask are adjacent to each other, and fabricating a first mask composed of the line portions and a second mask composed of the contact portions; a step of illuminating the resist through a first mask under a first illumination condition; and a step of illuminating the resist through a second mask under a second illumination condition. According to the description, dimensional errors of the final resist pattern ascribable to the optical proximity effect can be reduced.
[Patent Document 1] Japanese Laid-Open Patent Publication No. 2005-201967
[Patent Document 2] Japanese Laid-Open Patent Publication No. 2005-86119